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18-bit, 1.5 lsb inl, 400 ksps pulsar ? differential adc in msop/lfcsp data sheet ad7690 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2006C2014 analog devices, inc. all rights reserved. technical support www.analog.com features 18-bit resolution with no missing codes throughput: 400 ksps inl: 0.75 lsb typical, 1.5 lsb maximum (6 ppm of fsr) dynamic range: 102 db at 400 ksps oversampled dynamic range: 125 db at 1 ksps noise-free code resolution: 20 bits at 1 ksps effective resolution: 22.7 bits at 1 ksps sinad: 101.5 db at 1 khz thd: ?125 db at 1 khz true differential analog input range: vref 0 v to v ref with v ref up to vdd on both inputs no pipeline delay single-supply 5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface proprietary serial interface spi/qspi/microwire?/dsp compatible daisy-chain multiple adcs and busy indicator power dissipation 4.25 w at 100 sps 4.25 mw at 100 ksps standby current: 1 na 10-lead package: msop (msop-8 size) and 3 mm 3 mm lfcsp (sot-23 size) pin-for-pin compatible with lfcsp/msop pulsar adcs applications battery-powered equipment data acquisition seismic data acquisition systems dvms instrumentation medical instruments figure 1. integral nonlinearity vs. code application example figure 2. table 1. msop, lfcsp/sot-23 14-/16-/18-bit pulsar adc type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18-bit true differential ad7691 ad7690 ad7982 ad7982 ada4941 ada4841 16-bit true differential ad7684 ad7687 ad7688 ad7693 ada4941 ada4841 16-bit pseudo differential ad7680 ad7683 ad7685 ad7694 ad7686 ad7980 ada4841 14-bit pseudo differential ad7940 ad7942 ad7946 ada4841 general description the ad7690 1 is an 18-bit, successive approximation, analog-to- digital converter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 18-bit sampling adc with no missing codes, an internal conversion clock, and a versatile serial interface port. on the cnv rising edge, it samples the voltage difference between the in+ and in? pins. the voltages on these pins swing in opposite phase between 0 v and ref. the reference voltage, ref, is applied externally and can be set up to the supply voltage. the power of the ad7690 scales linearly with the throughput. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single, 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate vio supply. the ad7690 is housed in a 10-lead msop or a 10-lead lfcsp with operation specified from ?40c to +85c. 1 protected by u.s. patent 6,703,961. 1.5 ?1.5 0 262144 code inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 05792-025 65536 131072 196608 positive inl = +0.42lsb negative inl = ?0.6lsb ad7690 ref gnd vdd in+ in? vio sdi sck sdo cnv +1.8v to vdd 3- or 4-wire interface (spi, daisy chain, cs) +2.5 v to +5v 10v, 5v, ... +5 v ada4941-1 05792-001
ad7690 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application example ........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology ...................................................................................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 circuit information .................................................................... 12 converte r operation .................................................................. 12 typical connection diagram .................................................... 13 analog inputs .............................................................................. 14 driver amplifier choice ........................................................... 14 single - to - differential driver .................................................... 15 voltage reference input ............................................................ 15 power supply ............................................................................... 16 supplying the adc from the reference .................................. 16 digital interface .......................................................................... 16 cs mode, 3 - wire without busy indicator ............................. 17 cs mode, 3 - wire with busy indicator ................................... 18 cs mode, 4 - wire without busy indicator ............................. 19 cs mode, 4 - wire with busy indicator ................................... 20 chain mode without busy indicator ...................................... 21 chain mode with busy indicator ............................................. 22 application hints ........................................................................... 23 layout .......................................................................................... 23 evaluating the ad7690 performance ...................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 7 /14 rev. b to rev. c changed qfn (lfcsp) to lfcsp .............................. throughout changes to features section ............................................................ 1 added patent note, note 1 .............................................................. 1 changes to evaluating the ad 7690 performance section ........ 23 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 7 /11 rev. a to rev. b changes to common - mode input range min parameter ......... 3 added epad note to figure 6 and table 6 ................................... 7 upd ated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 3/07 rev. 0 to rev. a removed endnote regarding qfn package .................. universal changes to features .......................................................................... 1 changes to table 1 ............................................................................ 1 changes to figure 2 .......................................................................... 1 changes to gain error in table 2 .................................................... 3 change to gain error temperat ure drift in table 2 .................... 3 change to zero temperature drift in table 2 ............................... 3 changes to power dissipation in table 3 ....................................... 4 change to conversion time: cnv rising edge to data available in table 4 ............................................................................ 5 change to acquisition time in table 4 .......................................... 5 changes to figure 12 ......................................................................... 9 ch ange to figure 22 caption ........................................................ 11 changes to circuit information section ..................................... 12 change to table 7 ........................................................................... 13 change to endnote 1 of figure 26 ................................................ 13 added figure 29 ............................................................................. 14 changes to driver amplifier choice section ............................. 14 change to evaluating the ad 7690 s performance section ....... 23 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 4/06 revision 0: initial version rev. c | page 2 of 24
data sheet ad7690 specifications vdd = 4.75 v to 5.25 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise n oted. table 2 . parameter conditions min typ max unit resolution 18 bits analog input voltage range in+ to in? ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common - mode input range in+, in? v ref /2 ? 0.1 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 65 db leakage current at 25c acquisition phase 1 na input impedance 1 throughput conversion rate 0 400 ksps transient response full - scale step 400 ns accuracy no missing codes 18 bits integral linearity error ?1.5 0.75 +1.5 lsb 2 differential linearity error ?1 0.5 +1.25 lsb transition noise ref = vdd = 5 v 0.75 lsb gain error 3 ?40 2 +40 lsb gain error temperature drift 0.3 ppm/c zero error 3 ?0.8 +0.8 mv zero temperature drift 0.3 ppm/c power supply sensitivity vdd = 5 v 5% 0.25 lsb ac accuracy dynamic range v ref = 5 v 101 102 db 4 oversampled dynamic range 5 f in = 1 ksps 125 db signal - to - noise f in = 1 khz, v ref = 5 v 100 101.5 db f in = 1 khz, v ref = 2.5 v 94.5 96 db spurious - free dynamic range f in = 1 khz, v ref = 5 v ?125 db total harmonic distortion f in = 1 khz, v ref = 5 v ?125 db signal - to - (noise + distortion) f in = 1 khz, v ref = 5 v 100 101.5 db intermodulation distortion 6 115 db 1 see the analog inputs section. 2 lsb means least significant bit. with the 5 v input range, one lsb is 38.15 v. 3 see the terminology section. these specifications include full temperature range variation but not the error contribution from the external reference. 4 all specifications in db are referred to a full - scale input fs r . tested with an input signal at 0.5 db below full scale, unless otherwise specified. 5 dynamic range obtained by oversam pling the adc running at a through put f s of 400 ksp s, followed by postdigital filtering with an output word rate f o . 6 f in1 = 21.4 khz and f in 2 = 18.9 khz, with each tone at ?7 db b elow full scale . rev. c | page 3 of 24
ad7690 data sheet vdd = 4.75 v to 5.25 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 3 . parameter conditions min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 400 ksps, ref = 5 v 100 a sampling dynamics ?3 db input bandwidth 9 mhz aperture delay vdd = 5 v 2.5 ns digital inputs logic levels v il ?0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 18 bits , twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 4.75 5.25 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 1 , 2 vdd and vio = 5 v, 25c 1 50 na power dissipation vdd = 5 v, 100 sps throughput 4.25 w vdd = 5 v, 100 ksps throughput 4.25 5 mw vdd = 5 v, 400 ksps throughput 17 20 mw energy per conversion 50 nj/sample temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact an analog devices , inc., sales representative for the extended temperature range. rev. c | page 4 of 24
data sheet ad7690 timing specification s vdd = 4.75 v to 5.25 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 4 . 1 parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 2.1 s acquisition time t acq 400 ns time between conversions t cyc 2.5 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck 15 ns sck period (chain mode) t sck vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 4 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d17 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 10 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 3 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns 1 see figure 3 and figure 4 for load conditions. figure 3 . load circuit for digital interface timing figure 4. voltage levels for timing 500 a i ol 500 a i oh 1.4v to sdo c l 50pf 02968-002 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 02968-003 notes: 1. 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2. 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. rev. c | page 5 of 24
ad7690 data sheet absolute maximum rat ings table 5 . parameter rating analog inputs in+, 1 in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (10 - lead msop) 200c/w jc thermal impedance (10 - lead msop) 44c/w lead temperature range jedec j - std -20 1 see the analog inputs section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution rev. c | page 6 of 24
data sheet ad7690 rev. c | page 7 of 24 pin configurations and function descriptions figure 5. 10-lead msop pin configuration figure 6. 10-lead lfcsp pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part, chain or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in chain mode, the data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock in put. when the part is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 18 sck cycles. cs mode is selected if sdi is high during the cn v rising edge. in this mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). epad exposed pad. the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pa d be soldered to the ground plane. 1 ai = analog input, di = digital input, do = digital output, and p = power. ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7690 top view (not to scale) 05792-004 0 5792-005 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9sdi 8sck 7sdo 6 cnv top view (not to scale) ad7690 notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the ground plane.
ad7690 data sheet terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb befo re the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 25). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first tr ansition (from 100 ... 00 to 100 ... 01) should occur at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) should occur for an analog voltage 1? lsb below the nominal full scal e (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula: enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise - free code resolution noise - free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as: noise - free code resolutio n = log 2 (2 n / peak - to - peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum o f the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. t he value for dynamic range is expressed in decibels. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that is less than the nyquist frequency, excluding harmonics and d c. the value of snr is expressed in decibels. signal -to - (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but e xcluding dc. the value for sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient re sponse transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied. rev. c | page 8 of 24
data sheet ad7690 typical performance characteristics figure 7 . integral nonlinearity vs. code figure 8 . histogram of a dc input at the code center figure 9. fast f ourier t ransform plot figure 10 . differential nonlinearity vs. code figure 11 . histogram of a dc input at the code transition figure 12 . snr, thd vs. input level 1.5 ?1.5 0 262144 code inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 05792-025 65536 131072 196608 positive inl = +0.42lsb negative inl = ?0.6lsb 80k 0 55 code in hex counts 05792-037 70k 60k 50k 40k 30k 20k 10k 57 58 59 5a 5b 5c 5d 5e 5f 60 0 0 39 1991 18 0 0 2614 67198 31666 27546 vdd = ref = 5v 0 ?180 0 200 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 20 40 60 80 100 120 140 160 180 f s = 400ksps f in = 1.99khz snr = 101.4db thd = ?122db sfdr = 130db sinad = 101.3db 05792-026 1.0 ?1.0 0 code dnl (lsb) 0 0.5 ?0.5 65536 131072 196608 262144 05792-027 60k 0 code in hex counts 05792-039 50k 40k 30k 20k 10k 32 31 33 34 35 36 37 38 39 3a 3b 3c 0 0 2 533 263 3 0 0 11212 vdd = ref = 5v 12623 53936 52500 95 96 97 98 99 100 101 102 103 104 105 thd (db) 05792-047 input leve l (db) snr (db) ?10 ?8 ?6 ?4 ?2 0 ?130 ?128 ?126 ?124 ?122 ?120 ? 1 18 ? 1 16 ? 1 14 ? 1 12 ? 1 10 snr thd rev. c | page 9 of 24
ad7690 data sheet figure 13 . snr, sinad, and enob vs. reference voltage figure 14 . snr vs. temperature figure 15 . sinad vs. frequency figure 16 . thd, sfdr vs. reference voltage figure 17 . thd vs. temperature figure 18 . thd vs. frequency 104 92 2.3 5.5 reference voltage (v) snr, sinad (db) 102 100 98 96 94 20 14 enob (bits) 19 18 17 16 15 2.7 3.1 3.5 3.9 4.3 4.7 5.1 enob sinad snr 05792-029 103 95 ?55 125 temperature (c) snr (db) 102 101 100 99 98 97 96 ?35 ?15 5 25 45 65 85 105 v ref = 5v 05792-030 105 65 0 200 frequency (khz) sinad (db) 05792-043 50 100 150 v ref = 5v, ?10db 100 95 90 85 80 75 70 v ref = 5v, ?1db ?100 ?125 2.3 5.5 reference voltage (v) thd (db) 135 1 10 sfdr (db) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 ?105 ? 1 10 ? 1 15 ?120 130 125 120 1 15 thd sfdr 05792-031 ?90 ?130 ?55 125 temperature (c) thd (db) ?35 ?15 5 25 45 65 85 105 v ref = 5v ?100 ? 1 10 ?120 05792-032 ?60 ?130 0 200 frequency (khz) thd (db) 05792-044 ?70 ?80 ?90 ?100 ? 1 10 ?120 50 100 150 v ref = 5v, ?1db v ref = 5v, ?10db rev. c | page 10 of 24
data sheet ad7690 figure 19 . operating current vs. supply figure 20 . power - down current vs. temperature figure 21 . operating current vs. temperature figure 22 . zero and gain error vs. temperature figure 23 . t dsdo delay vs. capacitance load and supply 1000 0 supply (v) vdd operating current (a) 05792-041 4.50 5.50 750 500 250 f s = 100ksps vdd vio 4.75 5.00 5.25 temperature ( c) power-down current (na) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 vdd + vio 05792-033 1000 ?6 temperature (c) operating current (a) 05792-042 ?55 125 750 500 250 f s = 100ksps vdd vio ?35 ?15 5 25 45 65 85 105 6 ?6 temperature (c) zero, gain error (lsb) 05792-040 ?55 125 4 2 0 ?2 ?4 ?35 ?15 5 25 45 65 85 105 gain error zero error sdo capacitive load (pf) 120 0 20 40 60 80 100 t dsdo delay (ns) 25 20 15 10 5 0 vdd = 5v, 85c vdd = 5v, 25c 05792-034 rev. c | page 11 of 24
ad7690 data sheet theory of operation figure 24 . adc simplified schematic circuit information the ad7690 is a fast, low power, single - supply, precise, 18 - bit adc using a successive approximation architecture. the ad7690 is capable of converting 400,000 samples per second (400 ksps) and powers down between conversions. when operating at 1 ksps, for example, it consumes 50 w typically, ideal for battery - powered applications. the ad7690 provides the user with an on - chip track - and - hold and do es not exhibit pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7690 is specified from 4.75 v to 5.25 v and can be interfaced to any 1.8 v to 5 v dig ital logic family. it is housed in a 10 - lead msop or a tiny 10 - lead lfcsp that allows space savings and flexible configurations. it is pin - for - pin compatible with the 18 - bit ad7691 and ad7982 and the 16 - bit ad7687 , ad7688 , and ad7693 . converter operation the ad7690 is a successive approximation adc based on a charge redistribution dac. figure 24 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary - weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, termina ls of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? in puts. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the g nd input. therefore, the differential voltage between the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array bet ween gnd and ref, the comparator input varies by binary - weighted voltage steps (v ref /2, v ref /4 ... v ref /262,144). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the ad7690 has an on - board conversion clock, th e serial clock, sck, is not required for the conversion process. sw+ msb 65,536c in+ lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 131,072c sw? msb 65,536c lsb 4c 2c c c 131,072c 05792-006 rev. c | page 12 of 24
data sheet ad7690 transfer functions the ideal transfer characteristic for the ad7690 is shown in figure 25 and table 7 . figure 25 . adc ideal transfer function table 7 . output codes and ideal input voltages description analog input v ref 5 v digital outpu t code (he) fsr ? 1 lsb +4.999962 v 0x1ffff 1 midscale + 1 lsb +38.15 v 0x00001 midscale 0 v 0x00000 midscale ? 1 lsb ?38.15 v 0x3ffff ?fsr + 1 lsb ?4.999962 v 0x20001 ?fsr ?5 v 0x20000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical connection d iagram figure 26 shows an example of the recommended connection diagram for the ad7690 when multiple supplies are available. figure 26 . typical application diagram with multiple supplies 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 05792-007 ad7690 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interface 5 100nf 100nf 5v 10f 2 v+ v+ v? 1.8v to vdd ref 1 0 to v ref 15? 2.7nf 4 v+ v? v ref to 0 15? 2.7nf ada4841-2 3 ada4841-2 3 4 1 see voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). 3 see table 8 for additional recommended amplifiers. 4 optional filter. see analog input section. 5 see the digital interface section for most convenient interface mode. 05792-008 rev. c | page 13 of 24
ad7690 data sheet analog inputs figure 27 shows an equivalent circuit of the input structure of the ad7690 . the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this causes the diodes to become forward biased and start conducting current. these diodes can handle a forward - biased current of 130 ma maximum. for instan ce, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part. f igure 27 . equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. f igure 28 . analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ and in?) can be modeled as a parallel combination of the capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is p rimarily the pin capacitance. r in is typically 600 ? and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. w hen the source impedance of the driving circuit is low, the ad7690 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source imp edance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. f igure 29 . thd vs. analog input frequency and source resistance driver amplifier c hoice although the ad7690 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7690 . the noise from the driver is filtered by the ad7690 analog input circuits 1 - pole, low - pass filter made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7690 is 28 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + = ? ? + ? 2 db3 2 db3 2 )( 2 )( 2 28 28 log20 n n loss ne f ne f snr where: f ?3 db is the input bandwidth in megahertz of the ad7690 (9 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n+ and e n? are the equivalent input noise voltage densities of the op amps connected to in+ and in?, in nv/hz. this approximation can be used when the resistances around the amplifiers are smal l. if larger resistances are used, their noise contributions should also be root summed squared. ? for ac applications, the driver should have a thd performance commensurate with the ad7690 . c in r in d1 d2 c pin in+ or in gnd vdd 05792-009 90 40 1 10000 frequenc (khz) cmrr (db) 05792-036 10 100 1000 85 80 75 70 65 60 55 50 45 v ref = vdd = 5v 05792-047 frequenc (khz) thd (db) 0 90 130 125 120 115 110 105 100 95 90 85 80 10 20 30 40 50 60 70 80 v ref = vdd 5v rev. c | page 14 of 24
data sheet ad7690 rev. c | page 15 of 24 ? for multichannel multiplexed applications, the driver amplifier and the ad7690 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4 ppm). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at an 18-bit level and should be verified prior to driver selection. table 8. recommended driver amplifiers amplifier typical application ada4941-1 very low noise, low power single to differential ada4841-x very low noise, small, and low power ad8655 5 v single supply, low noise ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single supply, low power single-to-differential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4941-1 single-ended-to-differential driver allows for a differential input into the part. the schematic is shown in figure 30. r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2, and c f are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. for example, for the 10 v range with a 4 k impedance, r2 = 1 k and r1 = 4 k. r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc. the common mode should be set close to v ref /2; however, if single supply is desired, it can be set slightly above v ref /2 to provide some headroom for the ada4941-1 output stage. for example, for the 10 v range with a single supply, r3 = 8.45 k, r4 = 11.8 k, r5 = 10.5 k, and r6 = 9.76 k. figure 30. single-ended-to- differential driver circuit voltage reference input the ad7690 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (for example, a reference buffer using the ad8031 or the ad8605), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, a reference-decoupling capacitor with a value as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. ad7690 ref gnd vdd in+ 2.7nf 100nf 2.7nf in? +5v ref 10v, 5v, ... +5.2v +5.2v 15 ? 10f 15 ? r2 c f ada4941 r1 r3 100nf r5 r4 r6 05792-010
ad7690 data sheet rev. c | page 16 of 24 power supply the ad7690 uses two power supply pins: a core supply, vdd, and a digital input/output interface supply, vio. vio allows a direct interface with any logic between 1.8 v and v dd . to reduce the number of supplies needed, the vio and vdd pins can be tied together. the ad7690 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 31. figure 31. psrr vs. frequency the ad7690 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. this makes the part ideal for low sampling rates (even of a few hertz) and low battery-powered applications. figure 32. operating current vs. sample rate supplying the adc from the reference for simplified applications, the ad7690 , with its low operating current, can be supplied directly using the reference circuit shown in figure 33. the reference line can be driven by ? the system power supply directly. ? a reference voltage with enough current output capability, such as the adr43x . ? a reference buffer, such as the ad8031 , which can also filter the system power supply, as shown in figure 33. figure 33. example of application circuit digital interface though the ad7690 has a reduced number of pins, it offers flexibility in its serial interface modes. when in cs mode, the ad7690 is compatible with spi, qspi?, digital hosts, and dsps, for example, blackfin? adsp-bf53x or adsp-219x . in this mode, the ad7690 can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the ad7690 provides a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is selected. in either mode, the ad7690 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. the busy indicator feature is enabled ? in cs mode if cnv or sdi is low when the adc conversion ends (see figure 37 and figure 41). ? in chain mode if sck is high during the cnv rising edge (see figure 45). 95 65 1 10000 frequency (khz) psrr (db) 05792-035 90 85 80 75 70 10 100 1000 1000 10 0.1 0.001 10 1m sampling rate (sps) operating current (a) 05792-045 100 1k 100k 10k vdd = 5v vio 0.01 1 100 10000 ad8031 ad7690 vio ref vdd 10f 1f 10 ? 10k ? 5v 5v 5v 1f 1 05792-046 1 optional reference buffer and filter.
data sheet ad7690 rev. c | page 17 of 24 cs mode, 3-wire without busy indicator this mode is usually used when a single ad7690 is connected to an spi-compatible digital host. the connection diagram is shown in figure 34, and the corresponding timing is given in figure 35. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7690 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. figure 34. 3-wire cs mode without busy indicator connection diagram (sdi high) figure 35. 3-wire cs mode without busy indicator seri al interface timing (sdi high) cnv sck sdo sdi data in clk convert v io digital host ad7690 05792-011 sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 16 17 18 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 05792-012
ad7690 data sheet rev. c | page 18 of 24 cs mode, 3-wire with busy indicator this mode is usually used when a single ad7690 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 36, and the corresponding timing is given in figure 37. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad7690 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad7690 s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. figure 36. 3-wire cs mode with bu sy indicator connection diagram (sdi high) figure 37. 3-wire cs mode with busy indi cator serial interface timing (sdi high) data in irq clk convert vio digital host 47k? cnv sck sdo sdi v io ad7690 05792-013 sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq 05792-014
data sheet ad7690 rev. c | page 19 of 24 cs mode, 4-wire without busy indicator this mode is usually used when multiple ad7690 s are connected to an spi-compatible digital host. a connection diagram example using two ad7690 s is shown in figure 38, and the corresponding timing is given in figure 39. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7690 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance and another ad7690 can be read. figure 38. 4-wire cs mode without busy indicator connection diagram figure 39. 4-wire cs mode without busy indica tor serial interface timing data in clk cs1 convert cs2 digital host cnv sck sdo sdi cnv sck sdo sdi ad7690 ad7690 05792-015 sdo d17 d16 d15 d1 d0 t dis sck 123 343536 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 16 17 t sck t sckl t sckh d0 d17 d16 19 20 18 sdi(cs2) 05792-016
ad7690 data sheet rev. c | page 20 of 24 cs mode, 4-wire with busy indicator this mode is usually used when a single ad7690 is connected to an spi-compatible digital host, which has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this independence is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 40, and the corresponding timing is given in figure 41. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7690 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or sdi going high (whichever occurs first), sdo returns to high impedance. figure 40. 4-wire cs mode with busy indi cator connection diagram figure 41. 4-wire cs mode with busy indicator serial interface timing data in irq clk convert cs1 vio digital host 47k ? cnv sck sdo sdi ad7690 05792-017 sdo d17 d16 d1 d0 t dis sck 123 171819 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 05792-018
data sheet ad7690 rev. c | page 21 of 24 chain mode without busy indicator this mode can be used to daisy-chain multiple ad7690 s on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7690 s is shown in figure 42, and the corresponding timing is given in figure 43. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7690 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7690 s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. figure 42. chain mode without busy indicator connection diagram figure 43. chain mode without busy indicator serial interface timing clk convert data in digital host cnv sck sdo sdi cnv sck sdo sdi ad7690 b ad7690 a 05792-019 sdo a = sdi b d a 17 d a 16 d a 15 sck 1 2 3 34 35 36 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 16 17 t sck t sckl t sckh d a 0 19 20 18 sdi a = 0 sdo b d b 17 d b 16 d b 15 d a 1 d b 1d b 0d a 17 d a 16 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 05792-020
ad7690 data sheet rev. c | page 22 of 24 chain mode with busy indicator this mode can also be used to daisy-chain multiple ad7690s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7690 s is shown in figure 44, and the corresponding timing is given in figure 45. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7690 adc labeled c in figure 44) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7690 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n + 1 clocks are required to read back the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7690 s in the chain, provided the digital host has an acceptable hold time. figure 44. chain mode with bu sy indicator connection diagram figure 45. chain mode with busy indicator serial interface timing clk convert data in irq digital host cnv sck sdo sdi cnv sck sdo sdi cnv sck sdo sdi ad7690 b ad7690 c ad7690 a 0 5792-021 sdo a = sdi b d a 17 d a 16 d a 15 sck 123 39 53 54 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 417 t sck t sckh t sckl d a 0 19 38 18 sdo b = sdi c d b 17 d b 16 d b 15 d a 1 d b 1d b 0d a 17 d a 16 55 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 17 d c 16 d c 15 d a 1d a 0 d c 1d c 0d a 16 21 35 36 20 37 d b 1d b 0d a 17 d b 17 d b 16 t dsdosdi t ssckcnv t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi 05792-022
data sheet ad7690 application hints layout the printed circuit board that houses the ad7690 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7690 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the ad7690 is used as a shield. fast switching signa ls, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it can be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the ad7690 s. the ad7690 voltage reference input ref has a dynamic input impedance and should be d ecoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, the ad7690 vdd and vio power supplies should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7690 and connected using short, wide t races to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 46 and figure 47. evaluating the ad7690 perfo rmance other recommended layouts for the ad7690 are outlined in the documentation of the evaluatio n board ( e va l - ad7690 s d z ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the e va l - sdp - cb 1z . figure 46 . example layout of the ad7690 (top layer) figure 47 . example layout of the ad7690 (bottom layer) 05792-023 05792-024 rev. c | page 23 of 24
ad7690 data sheet outline dimensions figure 48 .10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters figure 49 . 10 - lead lead frame chip s cale package [ lfcsp_wd ] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 , 2 , 3 notes temperature range package description package option branding ordering quantity ad7690bcpzrl C 40c to +85c 10 - lead lfcsp_wd cp -10 -9 c4c reel, 5,000 ad7690bcpzrl7 C 40c to +85c 10 - lead lfcsp_wd cp -10 -9 c4c reel, 1,000 ad7690brmz C 40c to +85c 10 - lead msop rm -10 c4c tube, 50 ad7690brmz -rl7 C 40c to +85c 10 - lead msop rm -10 c4c reel, 1,000 eval - ad7690sd z evaluation board eval - sdp - cb1z controller board 1 z = rohs compliant part. 2 the eval - ad7690sdz board can be used as a stand alone evaluation board or in conjunction with the eval - sdp - cb1z for evaluation/demonstration purposes . 3 the eval - sdp - cb1z allows a pc to control and communicate with all analog devices evaluation boards ending in the sd designator. c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t op view bottom view 0.20 min ? 2006 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05792 - 0 - 7/14(c) rev. c | page 24 of 24

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